| 数据搜索系统,热门电子元器件搜索 |
|
M68AW512D 数据表(PDF) 3 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
M68AW512D 数据表(HTML) 3 Page - STMicroelectronics |
|
3 / 18 page ![]() 3/18 M68AW512D SUMMARY DESCRIPTION The M68AW512D is an 8 Mbit (8,388,608 bit) CMOS SRAM, organized as 524,288 words by 16 bits. The device features fully static operation re- quiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7 to 3.6V supply. This device has a Chip Select pin (E2) for easy memory expansion; when it is active (E2 high) the device has an automatic power-down feature, reducing the power con- sumption by over 99%. The M68AW512D is available in TFBGA48 (0.75 mm ball pitch) package. Figure 2. Logic Diagram Table 1. Signal Names AI04800b 19 A0-A18 W DQ0-DQ15 VCC M68AW512D G 16 E1 UB LB VSS E2 A0-A18 Address Inputs DQ0-DQ15 Data Input/Output E1 Chip Enable E2 Chip Select G Output Enable W Write Enable UB Upper Byte Enable Input LB Lower Byte Enable Input VCC Supply Voltage VSS Ground NC Not Connected DU Don’t Use as Internally Connected |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |