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March 2000

M68Z512

4 Mbit (512Kb x8) Low Power SRAM with Output Enable

s

ULTRA LOW DATA RETENTION CURRENT

– 100nA (typical)

–10µA (max)

s

OPERATION VOLTAGE: 5V ±10%

s

512 Kbit x8 SRAM with OUTPUT ENABLE

s

EQUAL CYCLE and ACCESS TIMES: 70ns

s

s

TRI-STATE COMMON I/O

s

CMOS for OPTIMUM SPEED/POWER

s

AUTOMATIC POWER-DOWN WHEN

DESELECTED

s

INTENDED FOR USE WITH ST

CONTROLLERS

DESCRIPTION

The M68Z512 is a 4 Mbit (4,194,304 bit) CMOS

SRAM, organized as 524,288 words by 8 bits. The

device features fully static operation requiring no

external clocks or timing strobes, with equal ad-

dress access and cycle times. It requires a single

5V ±10% supply, and all inputs and outputs are

TTL compatible.

This device has an automatic power-down feature,

reducing the power consumption by over 99%

when deselected.

The M68Z512 is available in a 32 lead TSOP II

(10 x 20mm) package.

Figure 1. Logic Diagram

AI03030

19

A0-A18

W

DQ0-DQ7

VCC

M68Z512

G

VSS

8

E

32

1

TSOP II 32 (NC)

10 x 20mm

Table 1. Signal Names

A0-A18

Address Inputs

DQ0-DQ7

Data Input/Output

E

Chip Enable

G

Output Enable

W

Write Enable

Supply Voltage

Ground