STMPE801

Interrupt, power supply & reset

17/26

8.2

Interrupt status GPIO register (ISGPIOR)

ISGPIOR register monitors the status of the interruption from a particular GPIO pin interrupt

source to the host. Regardless whether the IEGPIOR bits are enabled or not, the ISGPIOR

bits are still updated. The ISG[9:0] bits are the interrupt status bits correspond to the

GPIO[7:0] pins.

8.3

GPIO controller

A total of 8 GPIOs are available in the STMPE801 port expander IC. The GPIO controller

contains the registers that allow the host system to configure each of the pins as input or

output. Unused GPIOs should be configured as outputs to minimize the power consumption.

A group of registers are used to control the exact function of each of the 8 GPIO. The

registers and their respective address is listed in the following table.

ISGPIOR

Bit

7

6

5

4

3

2

1

0

ISG7

ISG6

ISG5

ISG4

ISG3

ISG2

ISG1

ISG0

R/W

RW

RW

RW

RW

RW

RW

RW

RW

Reset

Value

00

0

0

0

0

0

0

Table 14. Register

Bits

Name

Description

7:0

ISG[x]

Interrupt Status GPIO (where x = 7 to 0)

Read:

Interrupt Status of the GPIO[x]. Reading the register will clear any bits that

has been set to ‘1’

Write:

Writing to this register has no effects

Table 15. Register

Address

Register Name

Description

Auto-Increment

(during sequential R/W)

0x10

GPMR

GPIO monitor pin state register

Yes

0x11

GPSR

GPIO set pin state register

Yes

0x12

GPDR

GPIO set pin direction register

Yes