M74HC646

M74HC648

October 1993

HC648 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE, INV.)

HC646 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE)

B1R

(Plastic Package)

ORDER CODES :

M74HCXXXM1R

M74HCXXXB1R

M1R

(Micro Package)

INPUT AND OUTPUT EQUIVALENT CIRCUIT

PIN CONNECTIONS (top view)

GAB, GAB, CAB,

A, B

SAB, SBA, CBA

.

HIGH SPEED

.

LOW POWER DISSIPATION

.

HIGH NOISE IMMUNITY

.

OUTPUT DRIVE CAPABILITY

15 LSTTL LOADS

.

SYMMETRICAL OUTPUT IMPEDANCE

.

BALANCED PROPAGATION DELAYS

.

WIDE OPERATING VOLTAGE RANGE

.

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS646/648

DESCRIPTION

The M74HC646/648 are high speed CMOS OCTAL

BUS TRANSCEIVERS AND REGISTERS, (3-

STATE) fabricated in silicon gate C

ogy. They have the same high speed performance

of LSTTL combined with true CMOS low power con-

sumption.

These devices consist of bus transceiver circuits

with 3-state output, D-type flip-flops, and control cir-

cuitry arranged for multiplexed transmission of data

directly from the input bus or from the internal reg-

isters. Data on the A or B bus will be clocked into the

registers on the low-to-high transition of the appro-

priate clock pin (Clock AB - or Clock BA). Enable (G)

and direction (DIR) pins are provided to control the

transceiver functions. In the transceiver mode, data

present at the high-impedance port may be stored

in either register or in both.

The select controls (Select AB select BA) can multi-

plex stored and real-time (transparent mode) data.

The direction control determines which bus will re-

ceive data when enable G is active (low).

In the isolation mode (enable G high), ”A” data may

be stored in one register and/or ”B” data may be

stored in the other register. When an output function

is disabled, the input function is still enabled and

may be used to store and transmit data. Only one

of the two buses, A or B, may be driven at a time.

All inputs are equipped with protection circuits

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