M54HC75

M74HC75

December 1992

4 BIT D TYPE LATCH

B1R

(Plastic Package)

ORDER CODES :

M54HC75F1R

M74HC75M1R

M74HC75B1R

M74HC75C1R

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

PIN CONNECTIONS (top view)

NC =

No Internal

Connection

INPUT AND OUTPUT EQUIVALENT CIRCUIT

.

HIGH SPEED

.

LOW POWER DISSIPATION

.

HIGH NOISE IMMUNITY

.

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

.

SYMMETRICAL OUTPUT IMPEDANCE

.

BALANCED PROPAGATION DELAYS

.

WIDE OPERATING VOLTAGE RANGE

.

PIN AND FUNCTION COMPATIBLE WITH

54/74LS75

The M54/74HC75 is a high speed CMOS 4-BIT D-

TYPE LATCH fabricated in silicon gate C

nology. It has the same high speed performance of

LSTTL combined with true CMOS low power con-

sumption. It contains two groups of 2-bit latches con-

trolled by an enable input (G1

•2or G3•4). These two

latch groups can be used in different circuits. Each

latch has Q and Q outputs (1Q - 4Q and 1Q - 4Q).

The data applied to the data input is transfered to the

Q and Q outputs when the enable input is taken high

and the outputs will follow the data input as long as

the enable input is kept high. When the enable input

is taken low, the information data applied to the data

input is retained at the outputs. All inputs are

equipped with protection circuits against static dis-

charge and transient excess voltage.

DESCRIPTION

1/9