www.austriamicrosystems.com/LED-Driver-ICs/AS1112

Revision 1.13

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AS1112

Datasheet - D e t a i l e d D e s c r i p t i o n

Figure 10. Error Detection Timing (GS=FFFFHEX, DC=3FHEX)

Note:

The rising edge of LD latches new data into the internal registers depending on the logic level of the pin MODE. If the pin MODE is tied

GND, the greyscale registers are updated. If the pin MODE is tied to VCC, the dot correction registers are updated.

Delay Between Outputs (only for AS1112 and AS1112B)

The AS1112 uses graduated delay circuits between OUTn outputs. These circuits are contained in the constant-current driver block of the

AS1112 (see Figure 1 on page 1). The average-delay time is 30ns (typ).

The maximum delay is 450ns (typ) from OUT0 to OUT15. The delay scheme works by switching on and switching off each output channel. Thus

the on/off time of each channel is the same regardless of the delay. These delays prevent large inrush currents and switching noise that can

reduce bypass capacitance when the outputs are switched on.

OUTn Enable

All OUTn channels can be collectively switched off with one signal. When OEN is set to 1, all OUTn channels are disabled, regardless of the

device logic operations. The greyscale counter is also reset when OEN is set to 1.

When OEN is set to 0, all OUTn channels are in normal operation.

Setting Maximum Channel Current

The maximum output current per channel is programmed by a single resistor, RIREF, which is placed between pin IREF and GND. The voltage

on pin IREF is set by an internal band gap VIREF (1.24V typ). The maximum channel current is equivalent to the current flowing through RIREF

multiplied by a factor of 31.5. The maximum output current is calculated as:

Where:

VIREF = 1.24V;

RIREF = User-selected external resistor.

Figure 7 on page 7 shows the maximum output current IOUT versus RIREF, where RIREF is the value of the resistor between IREF terminal to

GND, and IOUT is the constant output current of OUT0:OUT15.

Table 9. Pin OEN Truth Table

OEN

OUT0:OUT15

0

Normal Operation

1

Disabled

LD

OEN

GSCLK

SID

>1µs

LODn, LSDn

LODn+1, LSDn+1

Error

Detection

Start

Error

Detection

End

IMAX =

VIREF

RIREF

x 31.5

(EQ 1)