AS3412 datasheet(51/85 Pages) AMSOSRAM

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[v1-00] 2016-Apr-06

AS3412 − Detailed Description

To keep the access time as short as possible, this format allows

a read access without the word address transfer in advance to

the data transfer. The bus is idle and the master issues a START

condition followed by the Device-Read address. Analogous to

Random Read, a single byte transfer is terminated with a

not-acknowledge after the 1st register byte. Analogous to

Sequential Read an unlimited number of data bytes can be

transferred, where the data bytes have to be responded with an

acknowledge from the master. For termination of the

transmission, the master sends a not-acknowledge following

the last data byte and a subsequent STOP condition.

Parameter

Figure 67:

I²C Serial Timing

I²C Serial Timing: This figure shows the I²C timing diagram.

1-7

ANC/CSDA

MODE/CSCL

1-7

Start

Condition

Address

R/W

ACK

Data

ACK

Data

ACK

Stop

Condition

T SU

T HD

T PD

AS3412 数据表(PDF) 51 Page - ams-OSRAM AG

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