AS3701 datasheet(54/110 Pages) AMSOSRAM

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ams Datasheet

Page 53

[v1-11] 2016-Dec-14

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AS3701 − Detailed Description – System Functions

Interrupt Generation

The interrupt controller generates an interrupt request for the

host controller as soon as one or more of the bits in the

InterruptMask registers are set by pulling low the pin XIRQ. All

the interrupt sources can be enabled in the Interrupt Mask

registers. If an interrupt occurs, the Interrupt Status registers

get set and cleared automatically after the host controller has

read them.

To prevent the AS3701 device from losing an interrupt event,

the register that is read is captured before it is transmitted to

the host controller via the serial interface. As soon as the

transmission of the captured value is completed, a logical AND

operation with the bit wise inverted captured value is applied

to the register to clear all interrupt bits that have already been

transmitted. Clearing the read interrupt bits takes 2 clock

cycles, a read access to the same register, before the clearing

process has completed, will yield a value of ‘0’. Note that an

interrupt that has been present at the previous read access will

be cleared as well in case it occurs again before the clearing

process has completed.

Wire-Serial Control Interface

Feature List

• Fast-mode capability (max. SCL-frequency is 400 kHz)

• 7+1-bit addressing mode

• 60h x 8-bit data registers (word address 0x00 - 0x60)

• Write formats: Single-Byte-Write, Page-Write

• Read formats: Current-Address-Read, Random-Read,

Sequential-Read

• SDA input delay and SCL spike filtering by integrated

RC-components

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