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AS7038RB 数据表(PDF) 50 Page - ams-OSRAM AG |
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AS7038RB 数据表(HTML) 50 Page - ams-OSRAM AG |
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50 / 127 page ![]() Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 49 Addr: 0x32 SEQ_START Bit Bit Name Default Access Bit Description 2 seq_start_gpio 0 R_PUSH After programming, the sequencer waits for a synchronization pulse via GPIO (see register GPIO_SYNC). For all released ADC channels a value is recorded per synchronization pulse (see register ADC_CHANNEL). 1 seq_start_sync 0 R_PUSH Similar to seq_start, but the sequencer will wait for overflow of the frequency divider that feeds all the switched-cap filters. This means 1) That it could take anything between 0 and 8 ms before the sequencer actually starts. 2) That the generated frequencies are in phase with the sequencer. For this to have any effect, the sequencer period should be selected with the selected frequencies (sd_bw, hp_freq) in mind. 0 seq_start 0 R_PUSH Writing 1 starts the sequencer(s) in the according to the configuration and upon rising edge of seq_start ADC selects first channel. Writing 0 stops the sequencer(s). In manual mode, writing 1 starts one ADC conversion but does not initialize the ADC channel selection. Reading returns 1 if the sequencer is running (sequencer mode), respectively if the ADC is converting (manual mode) With the SEQ_START register sets the configured sequencer can be started SEQ_PER (Address 0x33) Figure 45: SEQ_PER Register Addr: 0x33 SEQ_PER Bit Bit Name Default Access Bit Description 7:0 seq_period 0 RW t_period Sequencer period T = t_period * (seq_div+1) * 1 µs The SEQ_PER register sets one measurement cycle of the sequencer. |
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