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RZ/F 数据表(PDF) 62 Page - Renesas Technology Corp

部件名 RZ/F
功能描述  RZ 32 & 64-bit MPUs, RZ/G Series
PDF  65 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

RZ/F 数据表(HTML) 62 Page - Renesas Technology Corp

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RZ/Five Group
REVISION HISTORY
R01DS0488EJ0110 Rev.1.10
Page 62 of 65
Jun 30, 2025
REVISION HISTORY
RZ/Five Group DATASHEET
REVISION HISTORY
Description
Rev.
Date
Page
Summary
1.00
Dec 25, 2024
First edition issued
1.10
Jun 30, 2025 1. Overview
11
Figure 1.1 Configuration of LSI Internal Bus
Text, modified (MPU Bus → MCPU Bus)
SRC, deleted
3. Electrical Characteristics
18
Table 3.3 DC Characteristics (1) [3.3-V I/O]
Input leakage current, added
19
Table 3.7 DC Characteristics (5) [RGMII/MII]
Input logic low (Remarks: 1.8-V RGMII/MII): The Min value, modified
20
Table 3.9 DC Characteristics (7) [1.8 V I/O (SD, QSPI)]
Output logic high voltage: The Min value, modified
Output logic low voltage: The Max value, modified
22
Table 3.18 DC Characteristics (16) [ADC]
Full-scale error, Offset error, Analog input capacitance, Analog input resistance, External
capacitance, and External resistance, added
Note 1, added
23
Figure 3.4 Analog Input Equivalent Circuit, added
27
Table 3.21 SDHC AC Access Timing (SDR at 3.3-V Operation)
SD_CLK clock high level width, SD_CLK clock low level width, SD_CMD,SD_DATA output
delay: The Min values, modified
28
Table 3.22 eMMC Host Interface Timing (MMC Default 3.3-V Power Supply)
SD0_CLK clock cycle, SD0_CLK clock high level width, SD0_CLK clock low level width,
SD0_CMD/SDDAT output delay: The Min values, modified
28
Table 3.23 eMMC Host Interface Timing (MMC Default 1.8-V Power Supply)
SD0_CLK clock cycle, SD0_CLK clock high level width, SD0_CLK clock low level width:
The Min values, modified
SD0_CMD/SDDAT output delay: The Min and Max values, modified
29
3.5.3.2 eMMC host interface timing (HS-SDR), modified
30
Table 3.26 eMMC Host Interface Timing (HS200 1.8-V Power Supply Operation, Output
Load 15 pF)
SD0_CLK clock high level width, SD0_CLK clock low level width: The Min values, modified
SD0_CMD/SDDAT output delay: The Min and Max values, modified
36
Table 3.32 Ethernet-IF Access Timing (Ether RGMII)
Duty cycle for gigabit: The Min and Max values, modified
Note, modified



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