M95256 datasheet(6/39 Pages) STMICROELECTRONICS

6 / 39 page

M95256, M95128

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SIGNAL DESCRIPTION

During all operations, VCC must be held stable and

within the specified valid range: VCC(min) to

VCC(max).

All of the input and output signals must be held

High or Low (according to voltages of VIH, VOH, VIL

or VOL, as specified in Table 13. to Table 17.).

These signals are described next.

Serial Data Output (Q). This

output

signal is

used to transfer data serially out of the device.

Data is shifted out on the falling edge of Serial

Clock (C).

Serial Data Input (D). This input signal is used to

transfer data serially into the device. It receives in-

structions, addresses, and the data to be written.

Values are latched on the rising edge of Serial

Clock (C).

Serial Clock (C). This input signal provides the

timing of the serial interface. Instructions, address-

es, or data present at Serial Data Input (D) are

latched on the rising edge of Serial Clock (C). Data

on Serial Data Output (Q) changes after the falling

edge of Serial Clock (C).

Chip Select (S). When this input signal is High,

the device is deselected and Serial Data Output

(Q) is at high impedance. Unless an internal Write

cycle is in progress, the device will be in the Stand-

by Power mode. Driving Chip Select (S) Low se-

lects the device, placing it in the Active Power

mode.

After Power-up, a falling edge on Chip Select (S)

is required prior to the start of any instruction.

Hold (HOLD). The Hold (HOLD) signal is used to

pause any serial communications with the device

without deselecting the device.

During the Hold condition, the Serial Data Output

(Q) is high impedance, and Serial Data Input (D)

and Serial Clock (C) are Don’t Care.

To start the Hold condition, the device must be se-

lected, with Chip Select (S) driven Low.

Write Protect (W). The main purpose of this in-

put signal is to freeze the size of the area of mem-

ory that is protected against Write instructions (as

specified by the values in the BP1 and BP0 bits of

the Status Register).

This pin must be driven either High or Low, and

must be stable during all write instructions.

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