Clock operations

M48T86

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PF: periodic interrupt flag

The Periodic Interrupt Flag (PF) is a “Read only” bit which is set to a '1' when an edge is

detected on the selected tap of the divider chain. The RS3-RS0 bits establish the periodic

rate. PF is set to a '1' independent of the state of the PIE Bit. The IRQ signal is active and

will set the IRQF Bit. The PF Bit is cleared by a RST or a software READ of Register C.

AF: alarm flag

A '1' in the AF (Alarm Interrupt Flag) Bit indicates that the current time has matched the

alarm time. If the AIE Bit is also a '1,' the IRQ pin will go low and a '1' will appear in the IRQF

Bit. A RST or a READ of Register C will clear AF.

UF: update ended interrupt flag

The Update Ended Interrupt Flag (UF) Bit is set after each update cycle. When the UIE Bit is

set to a '1,' the '1' in the UF Bit causes the IRQF Bit to be a '1.' This will assert the IRQ pin.

UF is cleared by reading Register C or a RST.

BIT 0 through 3: unused bits

Bit 3 through Bit 0 are unused. These bits always read '0' and cannot be written.

Register D

VRT: valid RAM and time

The Valid RAM and Time (VRT) Bit is set to the '1' state by STMicroelectronics prior to

shipment. This bit is not writable and should always be a '1' when read. If a '0' is ever

present, an exhausted internal lithium cell is indicated and both the contents of the RTC

data and RAM data are questionable. This bit is unaffected by RST.

BIT 0 through 6: unused bits

The remaining bits of Register D are not usable. They cannot be written and when read,

they will always read '0.'

Table 7.

Register C MSB

Table 8.

Register D MSB

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

IRQF

PF

AF

UF

0000

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

VRT

0000000