R5F56517FDFM datasheet(32/188 Pages) RENESAS

32 / 188 page

RX65N Group, RX651 Group

1. Overview

R01DS0276EJ0240 Rev.2.40

Page 32 of 188

Oct 31, 2023

Ethernet controller

REF50CK0

Input

50-MHz reference clocks. These pins input reference signals for

transmission/reception timings in RMII mode.

RMII0_CRS_DV

Input

Indicate that there are carrier detection signals and valid

receive data on RMII0_RXD1 and RMII0_RXD0 in RMII mode.

RMII0_TXD0, RMII0_TXD1

Output

2-bit transmit data in RMII mode

RMII0_RXD0, RMII0_RXD1

Input

2-bit receive data in RMII mode

RMII0_TXD_EN

Output

Output pins for data transmit enable signals in RMII mode

RMII0_RX_ER

Input

Indicate an error has occurred during reception of data in RMII

mode.

ET0_CRS

Input

Carrier detection/data reception enable pins

ET0_RX_DV

Input

Indicate that there are valid receive data on ET0_ERXD3 to

ET0_ERXD0.

ET0_EXOUT

Output

General-purpose external output pins

ET0_LINKSTA

Input

Input link status from the PHY-LSI.

ET0_ETXD0 to ET0_ETXD3

Output

4 bits of MII transmit data

ET0_ERXD0 to ET0_ERXD3

Input

4 bits of MII receive data

ET0_TX_EN

Output

Transmit enable pins. Function as signals indicating that

transmit data is ready on ET0_ETXD3 to ET0_ETXD0.

ET0_TX_ER

Output

Transmit error pins. Function as signals notifying the PHY-LSI of

an error during transmission.

ET0_RX_ER

Input

Receive error pins. Function as signals to recognize an error

during reception.

ET0_TX_CLK

Input

Transmit clock pins. These pins input reference signals for

output timings from ET0_TX_EN, ET0_ETXD3 to ET0_ETXD0,

and ET0_TX_ER.

ET0_RX_CLK

Input

Receive clock pins. These pins input reference signals for input

timings to ET0_RX_DV, ET0_ERXD3 to ET0_ERXD0, and

ET0_RX_ER.

ET0_COL

Input

Input collision detection signals.

ET0_WOL

Output

Receive Magic packets.

ET0_MDC

Output

Output reference clock signals for information transfer via

ET0_MDIO.

ET0_MDIO

I/O

Input or output bidirectional signals for exchange of

management information between this MCU and the PHY-LSI.

USB 2.0 host/function

module

VCC_USB

Input

Power supply pin

VSS_USB

Input

Ground pin

USB0_DP

I/O

Input or output USB transceiver D+ data.

USB0_DM

I/O

Input or output USB transceiver D- data.

USB0_EXICEN

Output

Connect to the OTG power IC.

USB0_ID

Input

Connect to the OTG power IC.

USB0_VBUSEN

Output

USB VBUS power enable pins

USB0_OVRCURA/

USB0_OVRCURB

Input

USB overcurrent pins

USB0_VBUS

Input

USB cable connection/disconnection detection input pin

CAN module

CRX0, CRX1, CRX1-DS

Input

Input pins

CTX0, CTX1

Output

Output pins

Table 1.4

Pin Functions (5/8)

Classifications

Pin Name

I/O

Description

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R5F56517FDFM 数据表(PDF) 32 Page - Renesas Technology Corp

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