| 数据搜索系统,热门电子元器件搜索 |
|
RZ/T2M 数据表(PDF) 53 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
RZ/T2M 数据表(HTML) 53 Page - Renesas Technology Corp |
|
53 / 128 page ![]() Table 2.11 Permissible Output Currents Item Symbol Conditions Min. Typ. Max. Unit Permissible output low current (max. value per pin) IOL All output pins — — 12 mA Permissible output low current (total) ΣIOL Sum of all output pins — — 80 mA Permissible output high current (max. value per pin) IOH All output pins — — -12 mA Permissible output high current (total) ΣIOH Sum of all output pins — — -80 mA Note: All output current values shall be within the values in this table to ensure the reliability of this LSI. Table 2.12 Thermal Resistance value (Reference) Item Symbol Package Max. Unit Thermal Resistance Θja 320 pin FBGA 17 × 17 mm, 0.8-mm pitch 25.0 °C/W 225 pin FBGA 13 × 13 mm, 0.8-mm pitch 25.3 °C/W 176 pin LQFP (Exposed Die Pad) 24 × 24 mm, 0.5-mm pitch 15.6 °C/W 128 pin LQFP (Exposed Die Pad) 20 × 14 mm, 0.5-mm pitch 15.4 °C/W Ψjt 320 pin FBGA 17 × 17 mm, 0.8-mm pitch 0.30 °C/W 225 pin FBGA 13 × 13 mm, 0.8-mm pitch 0.31 °C/W 176 pin LQFP (Exposed Die Pad) 24 × 24 mm, 0.5-mm pitch 0.29 °C/W 128 pin LQFP (Exposed Die Pad) 20 × 14 mm, 0.5-mm pitch 0.30 °C/W Note: Package thermal resistance values above are based on EIA/JESD51-9 (2s2p) condition and reference only. 2.5 AC Characteristics Table 2.13 Operating frequency Parameter Symbol Min. Max. Unit Operating frequency CPU clock (CPUnCLK, n = 0, 1) f 150 200 600 800 MHz System clock (ICLK) 150 200 Peripheral module clock H (PCLKH) 150 200 Peripheral module clock M (PCLKM) 75 100 Peripheral module clock L (PCLKL) 37.5 50 Peripheral module clock for ADC (PCLKADC) 18.75 25 Peripheral module clock for SCIn (PCLKSCIn, n = 0 to 5) 75 100 Peripheral module clock for SPIn (PCLKSPIn, n = 0 to 3) 75 100 External bus clock output (CKIO) 18.75 100 Ethernet PHY reference clock (ETHn_REFCLK, n = 0 to 2) 25 Ethernet PHY reference clock (RMIIn_REFCLK, n = 0 to 2) 50 AC Characteristics are defined in condition of the IO setting (DRCTLm register setting) show in Table 2.14. RZ/T2M Datasheet 2. Electrical Characteristics R01DS0383EJ0130 Rev.1.30 Mar 13, 2026 Page 53 of 128 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |