9DB233

TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3

IDT®

TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3

7

9DB233

OCTOBER 20, 2016

Electrical Characteristics–PCIe Phase Jitter Parameters

TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Notes

tjphPCIeG1

PCIe Gen 1

34

86

ps (p-p)

1,2,3

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

13

ps

(rms)

1,2

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

2

3.1

ps

(rms)

1,2

tjphPCIeG3

PCIe Gen 3

(PLL BW of 2-4MHz, CDR = 10MHz)

1

1

ps

(rms)

1,2,4

tjphPCIeG1

PCIe Gen 1

2

5

ps (p-p)

1,2,3

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

0.2

0.3

ps

(rms)

1,2

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

0.1

0.2

ps

(rms)

1,2

tjphPCIeG3

PCIe Gen 3

(PLL BW of 2-4MHz, CDR = 10MHz)

0.1

0.2

ps

(rms)

1,2,4

1 Applies to all outputs.

4 Subject to final ratification by PCI SIG.

tjphPCIeG2

2 See http://www.pcisig.com for complete specs

tjphPCIeG2

Phase Jitter, PLL Mode

Additive Phase Jitter,

Bypass Mode

3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.