Device operation

M24512-x, M24256-Bx

16/35

3.9

ECC (error correction code) and write cycling

The M24xxx-W, M24xxx-R and M24xxx-HR devices offer an ECC (error correction code)

logic which compares each 4-byte word with its six associated ECC EEPROM bits. As a

result, if a single bit out of 4 bytes of data happens to be erroneous during a Read operation,

the ECC detects it and replaces it by the correct value. The read reliability is therefore much

improved by the use of this feature.

Note however that even if a single byte has to be written, 4 bytes are internally modified

(plus the ECC bits), that is, the addressed byte is cycled together with the other three bytes

making up the word. It is therefore recommended to write by word (4 bytes) in order to

benefit from the larger amount of Write cycles.

The M24xxx-W, M24xxx-R and M24xxx-HR devices are qualified at 1 million (1 000 000)

Write cycles, using a cycling routine that writes to the device by multiples of 4-bytes.

Figure 8.

Write Mode sequences with WC = 0 (data write enabled)

Byte Write

Dev sel

Byte addr

Byte addr

Data in

WC

Page Write

Dev sel

Byte addr

Byte addr

Data in 1

WC

Data in 2

AI01106d

Page Write

(cont'd)

WC (cont'd)

Data in N

ACK

R/W

ACK

ACK

ACK

ACK

ACK

ACK

ACK

R/W

ACK

ACK