PSD4235G2 datasheet(30/89 Pages) STMICROELECTRONICS

30 / 89 page

PSD4235G2

30/89

Figure 10. 8031 Memory Modules – Combined Space

Page Register

The 8-bit Page Register increases the addressing

capability of the MCU by a factor of up to 256. The

contents of the register can also be read by the

MCU. The outputs of the Page Register (PGR0-

PGR7) are inputs to the DPLD decoder and can be

included

the

Sector

Select

(FS0-FS7,

CSBOOT0-CSBOOT3), and SRAM Select (RS0)

equations.

If memory paging is not needed, or if not all eight

page register bits are needed for memory paging,

these bits may be used in the CPLD for general

logic. See Application Note

AN1154.

Table 22 and Figure 11 show the Page Register.

The eight flip-flops in the register are connected to

the internal data bus (D0-D7). The MCU can write

to or read from the Page Register. The Page Reg-

ister can be accessed at address location CSIOP

+ E0h.

Figure 11. Page Register

Primary

Flash

Memory

DPLD

Secondary

Flash

Memory

SRAM

RS0

CSBOOT0-3

FS0-FS7

VM REG BIT 2

PSEN

VM REG BIT 0

VM REG BIT 1

VM REG BIT 3

VM REG BIT 4

AI02870C

RESET

D 0-D 7

R/W

PAGE

PGR0

PGR1

PGR2

PGR3

DPLD

AND

CPLD

INTERNAL

SELECTS

AND LOGIC

PLD

PGR4

PGR5

PGR6

PGR7

AI02871B

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