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RIVA128ZX 数据表(PDF) 21 Page - STMicroelectronics |
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RIVA128ZX 数据表(HTML) 21 Page - STMicroelectronics |
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21 / 85 page  128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX 21/85 AGP timing specification Figure 12. AGP clock specification Table 1. AGP clock timing parameters NOTES 1 This rise and fall time is measured across the minimum peak-to-peak range as shown in Figure 12. Figure 13. AGP timing diagram Table 2. AGP timing parameters Symbol Parameter Min. Max. Unit Notes tCYC PCICLK period 15 30 ns tHIGH PCICLK high time 6 ns tLOW PCICLK low time 6 ns PCICLK slew rate 1.5 4 V/ns 1 Symbol Parameter Min. Max. Unit Notes tVAL AGPCLK to signal valid delay (data and control signals) 211 ns tON Float to active delay 2 ns tOFF Active to float delay 28 ns tSU Input set up time to AGPCLK (data and control signals) 7ns tH Input hold time from AGPCLK 0ns tCYC tHIGH tLOW PCICLK 0.3VDD 0.4VDD 0.5VDD 0.2VDD 0.6VDD 2V p-to-p (minimum) tVAL tVAL tON tOFF tSU tH data1 data2 data1 data2 AGPCLK Output delay Tri-state output Input |
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