DM9010
Single Chip Ethernet Controller with General Processor Interface
Preliminary
39
Version: DM9010-DS-P03
Apr. 28, 2005
After auto-negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 100M half
duplex mode. The software can read bit [15:12] to see which mode
is selected after auto-negotiation. This bit is invalid when it is not in
the auto-negotiation mode
17.13
10FDX
1, RO
10M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 10M Full
Duplex mode. The software can read bit [15:12] to see which mode
is selected after auto-negotiation. This bit is invalid when it is not in
the auto-negotiation mode
17.12
10HDX
1, RO
10M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 10M half
duplex mode. The software can read bit [15:12] to see which mode
is selected after auto-negotiation. This bit is invalid when it is not in
the auto-negotiation mode
17.11-17
.9
Reserved
0, RO
Reserved
Read as 0, ignore on write
17.8-17.
4
PHYADR
[4:0]
1, RW
PHY Address Bit 4:0
The first PHY address bit transmitted or received is the MSB of the
address (bit 4). A station management entity connected to multiple
PHY entities must know the appropriate address of each PHY
17.3-17.
0
ANMB[3:
0]
0, RO
Auto-negotiation Monitor Bits
These bits are for debug only. The auto-negotiation status will be
written to these bits.
B3 b2 b1 B0
0
0
0
0
In IDLE state
0
0
0
1
Ability match
0
0
1
0
Acknowledge match
0
0
1
1
Acknowledge match fail
0
1
0
0
Consistency match
0
1
0
1
Consistency match fail
0
1
1
0
Parallel detects signal_link_ready
0
1
1
1
Parallel detects signal_link_ready fail
8.10 10BASE-T Configuration/Status (10BTCSR) - 18
Bit
Bit Name
Default
Description
18.15
Reserved
0, RO
Reserved
Read as 0, ignore on write
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