DM9010
Single Chip Ethernet Controller with General Processor Interface
Preliminary
13
Version: DM9010-DS-P03
Apr. 28, 2005
5.3 EEPROM Interface
64
EEDI
I
Data from EEPROM
65
EEDO
O,PD Data to EEPROM
This pin is also used as a strap pin. It combines with strap pin WOL, and
it can set the data width of the internal memory access
The decoder table is the following, where the logic 1 means the strap pin
is pulled high
WAKE
EEDO
data width
0
0
16-bit
0
1
32-bit
1
0
8-bit
1
1
reserved
66
EECK
O,PD Clock to EEPROM
67
EECS
O,PD Chip Select to EEPROM
This pin is also used as a strap pin to define the LED modes.
When it is pulled high, the LED mode is mode 1; Otherwise it is mode 0
Note: The pins EECS,EECK and EEDO are all have a pulled down resistor about 60k ohm internally
5.4 Clock Interface
21
X2_25M
O
Crystal 25MHz Out
22
X1_25M
I
Crystal 25MHz In
59
CLK20MO
I/O,PD 20Mhz Clock Output
It is used as the clock signal for the external MII device’s clock is 20MHz
This pin has a pulled down resistor about 60k ohm internally.
When pin TEST5 state is high, this pin act as the system clock.
5.5 LED Interface
60
SPLED
O
Speed LED
Its low output indicates that the internal PHY is operated in 100M/S, or it
is floating for the 10M mode of the internal PHY
61
FDLED
O
Full-duplex LED
In LED mode 1, Its low output indicates that the internal PHY is operated
in full-duplex mode, or it is floating for the half-duplex mode of the
internal PHY
In LED mode 0, Its low output indicates that the internal PHY is operated
in 10M mode, or it is floating for the 100M mode of the internal PHY
62
LKLED
O
Link / Active LED
In LED mode 1, it is the combined LED of link and carrier sense signal of
the internal PHY
In LED mode 0, it is the LED of the carrier sense signal of the internal
PHY only
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