CS5543 datasheet(21/30 Pages) CIRRUS

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CS5542 CS5543

DS109PP2

The instruction register is used to select the test to

be performed or to select the test data register to be

accessed. The 3-bit instructions available in the in-

struction register are illustrated in Table 6. The

LSB of the 3-bit instruction is shifted in first.

Table 6. Boundary Scan Instructions

Several test registers are in the design including the

Boundary-Scan Register (BSR), the Device Identi-

fication Register (DIR), the Operating Mode Reg-

ister (OMR), and the Bypass Register (BR).

The Boundary-Scan Register allows for the testing

of board interconnects. The bit ordering for the

BSR is the same as the top-view packaged pinout,

clockwise beginning with the MDATA[3], and

ending with RST. The TAP, power and gnd pins

are not included as part of the boundary-scan regis-

ter. The BSR is 47 bits long. Inputs can be set via

the BSR, bypassing the actual pin. All outputs are

3-state (logic high, low and or high impedance)

outputs. Their states during test can be controlled

via the PRELOAD instruction. In the boundary-

scan register, each input pin of the device is repre-

sented by one bit position of the boundary scan reg-

ister, whereas each of the outputs, having the

possibility of any one of three states, require two

bits each in the boundary-scan register.

The Device Identification Register is designed to

identify the manufacturer, the part number, and the

version number of the CS5543. The format of the

DIR is illustrated in Table 7. Data from the DIR is

shifted out of the TDO LSB first. Note that when

the CS5543 is reset, the Instruction Register is set

to select IDCODE.

IR CODE

INSTRUCTION

000

001

010

011

100

101

110

111

EXTEST

SAMPLE/PRELOAD

IDCODE

OPERATING MODE REGISTER

reserved

BYPASS

Test-Logic-Reset

Run-Test/Idle

Capture-DR

Select-DR-Scan

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Capture-IR

Select-IR-Scan

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

Figure 8. TPA Controller State Diagram

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