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74HCT573PW 数据表(PDF) 4 Page - Nexperia B.V. All rights reserved |
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74HCT573PW 数据表(HTML) 4 Page - Nexperia B.V. All rights reserved |
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4 / 20 page ![]() 74HC_HCT573 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet Rev. 7 — 4 March 2016 4 of 20 NXP Semiconductors 74HC573; 74HCT573 Octal D-type transparent latch; 3-state 5. Pinning information 5.1 Pinning 5.2 Pin description (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 5. Pin configuration SO20, SSOP20 and TSSOP20 Fig 6. Pin configuration DHVQFN20 Table 2. Pin description Symbol Pin Description OE 1 3-state output enable input (active LOW) D[0:7] 2, 3, 4, 5, 6, 7, 8, 9 data input GND 10 ground (0 V) LE 11 latch enable input (active HIGH) Q[0:7] 19, 18, 17, 16, 15, 14, 13, 12 3-state latch output VCC 20 supply voltage |
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