ADATE320 datasheet(52/78 Pages) AD

52 / 78 page

Data Sheet

ADATE320

THEORY OF OPERATION

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The ADATE320 is configured through a collection of 16-bit registers

as defined in Table 29. Mode configuration, DAC level settings,

calibration constants, and alarm flags status can all be controlled

and monitored by accessing the respective registers.

Specific access to any 16-bit register is made through a serial pro-

grammable interface (SPI). A single SPI control register is exposed

to the user by this hardware SPI interface. The format of the SPI

Control Register is illustrated in Figure 128. The SPI control register

includes address and channel information, read/write direction, and

a 16-bit data field. Any valid SPI write instruction cycle populates

all these fields, and the ADATE320 subsequently operates on the

addressed channel and register using the data provided. Any valid

SPI read instruction cycle populates only the address and channel

fields, and the ADATE320 makes the addressed register contents

in the 16-bit data field available for subsequent readout at the SDO

pin.

Detailed SPI timing diagrams for each read/write operation type are

provided in Figure 2 through Figure 7. Respective dc and ac timing

parameters are provided in Table 13 and Table 14, respectively.

A typical hardware wiring diagram for the SPI is illustrated in Figure

127.

LEVEL SETTING DACS

DAC Update Modes

The ADATE320 provides 32 16-bit integrated level setting DACs

organized as two channel banks of 16 DACs each. The detailed

mapping of each DAC register to each pin electronics function is

shown in Table 29. Each DAC can be individually programmed by

writing data to the respective SPI register address and channel.

The ADATE320 provides two methods for updating analog DAC

levels: DAC immediate update mode and DAC deferred update

mode. At the release of the CS pin associated with any valid SPI

write to a DAC address, the update of the analog levels can start

immediately or can be deferred, depending on the state of the

DAC_LOAD_MODE control bit in the DAC control register (see

Figure 145). Initiation of the analog level update sequence (and

triggering of the on-chip deglitch circuit) begins four SCLK cycles

following the associated release of CS pin. For the purpose of this

data sheet, the analog level update sequence is assumed to start

coincident with the release of CS. The DAC update mode can be

selected independently for each channel bank.

If the DAC_LOAD_MODE control bit for a given channel bank is

cleared, the DACs assigned to that channel bank are placed in

the DAC immediate update mode. Writing to any DAC within that

channel causes the corresponding analog levels to be updated

immediately following the associated release of CS. Because all

analog levels are updated on a per channel basis, any previously

pending DAC writes queued to that channel (while in an earlier

deferred update mode) are also updated at this time. This situation

can arise if DAC writes are queued to the channel while in deferred

update mode, and then the DAC_LOAD_MODE bit is subsequently

changed to immediate update mode before writing to the respective

DAC_LOAD control bit (see Figure 145). The queued data is not

lost. Note that writing to the DAC_LOAD control bit has no effect

while in immediate update mode.

If the DAC_LOAD_MODE control bit for a given channel is set, then

the DACs assigned to that channel bank is in the deferred update

mode. Writing to any DAC of that channel only queues the DAC

data into that channel. The analog update of queued DAC levels

is deferred until the respective DAC_LOAD control bit is set (see

Figure 145). The DAC deferred update mode, in conjunction with

the respective DAC_LOAD control bit, provides the means to queue

all DAC level writes to a given channel bank before synchronously

updating the analog levels with a single SPI command.

The OVDH and OVDL DAC levels do not fit neatly within a particu-

lar channel bank. However, they must be updated as a part of the

channel bank to which they are assigned, as shown in Table 29.

The ADATE320 provides a feature in which a single SPI write

operation can address two channels at one time. With this feature,

a single SPI write operation can address corresponding DACs on

both channels at the same time, even though the channels may

be configured with different DAC update modes. In such a case,

the device behaves as expected. For example, if both channels

are in immediate update mode, the update of analog levels of both

channel banks begins following the associated release of the CS

pin. If both channels are in deferred update mode, the update of

analog levels is deferred for both channels until the corresponding

DAC_ LOAD control bit is set. If one channel is in deferred update

mode and the other is in immediate update mode, the deferred

channel defers analog updates until the corresponding DAC_LOAD

bit is written, and the immediate channel begins analog updates

immediately following release of the CS pin.

An on-chip deglitch circuit with a period of approximately 3 µs is

provided to prevent DAC-to-DAC crosstalk within a channel when-

ever an analog update is processed. Each DAC channel bank has

its own dedicated deglitch circuitry, and each channel may therefore

operate independently.

A deglitch circuit can be retriggered if an analog level update

is initiated before a previous update operation on that channel

completes. Analog transitions at the DAC outputs do not begin until

after the deglitch circuit times out. Final settling to full precision

requires an additional 7 µs beyond the end of the 3 µs deglitch

interval. The total DAC settling time following the release of the

associated CS pin is approximately 10 µs maximum. Note that

an extended retriggering sequence of the deglitch circuit on one

channel may cause the apparent settling time of analog levels on

that channel to appear delayed longer than the specified 10 µs.

A typical DAC update sequence is illustrated in Figure 129. In this

example, consecutive immediate mode DAC updates are written in

direct succession. This example was chosen to illustrate what hap-

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