74LVC08A

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© NXP Semiconductors N.V. 2016. All rights reserved.

Product data sheet

Rev. 7 — 19 April 2016

2 of 15

NXP Semiconductors

74LVC08A

Quad 2-input AND gate

4.

Functional diagram

5.

Pinning information

5.1 Pinning

Fig 1.

Logic symbol

Fig 2.

IEC logic symbol

Fig 3.

Logic diagram for one gate

(1) This is not a supply pin. The substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land should remain

floating or be connected to GND.

Fig 4.

Pin configuration SO14 and (T)SSOP14

Fig 5.

Pin configuration DHVQFN14

74LVC08A

1A

VCC

1B

4B

1Y

4A

2A

4Y

2B

3B

2Y

3A

GND

3Y

001aac945

1

2

3

4

5

6

7

8

10

9

12

11

14

13

001aac946

74LVC08A

GND(1)

Transparent top view

2Y

3A

2B

3B

2A

4Y

1Y

4A

1B

4B

6

9

5

10

4

11

3

12

2

13

terminal 1

index area