ST10F269Z2QX datasheet(108/161 Pages) STMICROELECTRONICS

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ST10F269Z2Qx

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Figure 55 : Asynchronous Reset Sequence Internal Fetch

Note: 1) RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on

(fCPU =fXTAL / 2), else it is 4 CPU clock cycles (8 TCL).

2) 2.1µs typical value.

Power-on reset

The asynchronous reset must be used during the power-on of the MCU. Depending on the crystal frequency,

the on-chip oscillator needs about 10ms to 50ms to stabilize. The logic of the MCU does not need a stabi-

lized clock signal to detect an asynchronous reset, so it is suitable for power-on conditions. To ensure a

proper reset sequence, the RSTIN pin and the RPD pin must be held at low level until the MCU clock sig-

nal is stabilized and the system configuration value on PORT0 is settled.

Hardware reset

The asynchronous reset must be used to recover from catastrophic situations of the application. It may be

triggered by the hardware of the application. Internal hardware logic and application circuitry are

described in Section 18.6 - Reset Circuitry and Figure 58, Figure 59 and Figure 60.

18.1.2 - Synchronous Reset (RSTIN pulse > 1040TCL and RPD pin at high level)

The synchronous reset is a warm reset. It may be generated synchronously to the CPU clock. To be

detected by the reset logic, the RSTIN pulse must be low at least for 4 TCL (2 periods of CPU clock).

Then the I/O pins are set to high impedance and RSTOUT pin is driven low. After the RSTIN level is

detected, a short duration of 12 TCL (6 CPU clocks) maximum elapses, during which pending internal

hold states are cancelled and the current internal access cycle, if any, is completed. External bus cycle is

aborted.

The internal pull-down of RSTIN pin is activated if bit BDRSTEN of SYSCON register was previously set

by software. This bit is always cleared on power-on or after any reset sequence.

The internal sequence lasts for 1024 TCL (512 periods of CPU clock). After this duration the pull-down of

RSTIN pin for the bidirectional reset function is released and the RSTIN pin level is sampled. At this step

the sequence lasts 1040 TCL (4 TCL + 12 TCL + 1024 TCL). If the RSTIN pin level is low, the reset

sequence is extended until RSTIN level becomes high. Refer to Figure 56

Note

If VRPD voltage drops below the RPD pin threshold (typically 2.5V for VDD = 5V) when RSTIN pin

is low or when RSTIN pin is internally pulled low, the ST10 reset circuitry disables the bidirectional

reset function and RSTIN pin is no more pulled low. The reset is processed as an asynchronous

reset.

6 or 8 TCL 1)

CPU Clock

RSTIN

Asynchronous

Reset Condition

RPD

RSTOUT

PORT0

Reset Configuration

INTERNAL FETCH

Internal reset signal

Flash read signal

PLL factor

latch command

Flash under reset for internal charge pump ramping up

1st fetch

from Flash

Latching point of PORT0

for PLL configuration

Latching point of PORT0

for remaining bits

2.5µs max.2)

ST10F269Z2QX 数据表(PDF) 108 Page - STMicroelectronics

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