ST10F269Z2QX datasheet(112/161 Pages) STMICROELECTRONICS

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(50k

Ω to 250kΩ), must lead to a charging time long enough to let the internal or external oscillator and /

or the on-chip PLL to stabilize.

The R0-C0 components on RPD pin are mainly implemented to provide a time delay to exit Power down

mode (see Chapter 19 - Power Reduction Modes). Nevertheless, they drive RPD pin level during resets

and they lead to different reset modes as explained hereafter. On power-on, C0 is total discharged, a low

level on RPD pin forces an asynchronous hardware reset. C0 capacitor starts to charge through R0 and

at the end of reset sequence ST10F269Z2Qx restarts. RPD pin threshold is typically 2.5V.

Depending on the delay of the next applied reset, the MCU can enter a synchronous reset or an

asynchronous reset. If RPD pin is below 2.5V an asynchronous reset starts, if RPD pin is above 2.5V a

synchronous reset starts. (See Section 18.1 - Long Hardware Reset and Section 18.2 - Short Hardware

Reset).

Note that an internal pull-down is connected to RPD pin and can drive a 100

µA to 200µA current. This

Pull-down is turned on when RSTIN pin is low.

To properly use the bidirectional reset features, the schematic (or equivalent) of Figure 60 must be

implemented. R1-C1 only work for power-on or manual reset in the same way as explained previously. D1

diode brings a faster discharge of C1 capacitor at power-off during repetitive switch-on / switch-off

sequences. D2 diode performs an OR-wired connection, it can be replaced with an open drain buffer. R2

resistor may be added to increase the pull-up current to the open drain in order to get a faster rise time on

RSTIN pin when bidirectional function is activated.

The start-up configurations and some system features are selected on reset sequences as described in

Table 29 and Table 30.

Table 29 describes what is the system configuration latched on PORT0 in the five different reset ways.

Table 30 summarizes the state of bits of PORT0 latched in RP0H, SYSCON, BUSCON0 registers.

Figure 58 : Internal (simplified) Reset Circuitry.

RSTOUT

EINIT Instruction

Trigger

Clr

Clock

Reset State

Machine

Internal

Reset

Signal

Reset Sequence

(512 CPU Clock Cycles)

SRST instruction

watchdog overflow

RSTIN

VDD

BDRSTEN

VDD

RPD

Weak pull-down

(~200

µA)

From/to Exit

Powerdown

Circuit

Asynchronous

Reset

Clr

Set

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