ST10F269Z2Q3 datasheet(114/161 Pages) STMICROELECTRONICS

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ST10F269Z2Qx

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19 - POWER REDUCTION MODES

Two

different

power

reduction

modes

with

different levels of power reduction have been

implemented in the ST10F269Z2Qx. In Idle mode

only CPU is stopped, while peripheral still

operate. In Power Down mode both CPU and

peripherals are stopped.

Both mode are software activated by a protected

instruction and are terminated in different ways as

described in the following sections.

Note:

All external bus actions are completed

before Idle or Power Down mode is

entered. However, Idle or Power Down

mode is not entered if READY is enabled,

but has not been activated (driven low for

negative

polarity, or

driven

high

for

positive polarity) during the last bus

access.

19.1 - Idle Mode

Idle mode is entered by running IDLE protected

instruction. The CPU operation is stopped and the

peripherals still run.

Idle mode is terminate by any interrupt request.

Whatever the interrupt is serviced or not, the

instruction following the IDLE instruction will be

executed

after

return

from

interrupt

(RETI)

instruction, then the CPU resumes the normal

program.

Note that a PEC transfer keep the CPU in Idle

mode. If the PEC transfer does not succeed, the

Idle mode is terminated. Watchdog timer must be

properly programmed to avoid any disturbance

during Idle mode.

19.2 - Power Down Mode

Power Down mode starts by running PWRDN

protected instruction. Internal clock is stopped, all

MCU parts are on hold including the watchdog

timer.

There are two different operating Power Down

modes: protected mode and interruptible mode.

The internal RAM contents can be preserved

through the voltage supplied via the VDD pins. To

verify RAM integrity, some dedicated patterns

may be written before entering the Power Down

mode and have to be checked after Power Down

is resumed.

It is mandatory to keep VDD = +5V ±10% during

power-down

mode,

because

the

on-chip

voltage regulator is turned in power saving

mode and it delivers 2.5V to the core logic, but

it must be supplied at nominal VDD = +5V.

19.2.1 - Protected Power Down Mode

This mode is selected when PWDCFG (bit 5) of

SYSCON register is cleared. The Protected

Power Down mode is only activated if the NMI pin

is pulled low when executing PWRDN instruction

(this means that the PWRD instruction belongs to

the NMI software routine). This mode is only

deactivated with an external hardware reset on

RSTIN pin.

Note: During power down the on-chip voltage

regulator automatically lowers the internal

logic supply voltage to 2.5V, to save power

and to keep internal RAM and registers

contents.

19.2.2 - Interruptible Power Down Mode

This mode is selected when PWDCFG (bit 5) of

SYSCON register is set (See Chapter 20 - Special

Function Register Overview).

The Interruptible Power Down mode is only

activated if all the enabled Fast External Interrupt

pins are in their inactive level (see EXICON

This mode is deactivated with an external reset

applied to RSTIN pin or with an interrupt request

applied to one of the Fast External Interrupt pins.

To allow the internal PLL and clock to stabilize,

the RSTIN pin must be held low according

the recommendations described in Chapter 18 -

System Reset.

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