ST16CF54 Level B

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DESCRIPTION

The ST16CF54 Level B, a member of the ST16

device family, is a serial access microcontroller

especially designed for high volume and cost

competitive Smartcard applications, where high

performance Public Key Algorithms will be imple-

mented, to cut down initialization and communica-

tion costs and to increase security.

Its internal Modular Arithmetic Processor is de-

signed to speed up cryptographic calculations re-

quired in Public Key Algorithms. It processes

hardware modular multiplication and squaring on

various size 32/256/288/384/416/512 bits oper-

and. By using of software (cryptographic firmware

library) this calculation can be extended for any

size of operand from 3 to 1024 bits. The

ST16CF54 Level B is based on an ST 8 bit CPU

core including on-chip memories: 512 Bytes of

RAM, 16 KBytes of USER ROM and 4 KBytes of

EEPROM.

Both ROM and EEPROM memories can be con-

figured into two sectors. Access rules from any

memory section (sector) to another are setup by

the User defined Memory Access Control Matrix.

In addition, to reinforce the security of this product,

an hardware mechanism called SRAC (SYSTEM

ROM Access Control) has been implemented. It

protects against unauthorized access to both

SYSTEM ROM and MAP.

Reliability data related to the ST16CF54 Level B

product, manufactured using ST’s advanced

CMOS EEPROM technology, confirm data reten-

tion of up to 10 years and endurance up to

100,000 Erase/Write cycles.

As all other ST16 family members, it is fully com-

patible with the ISO standards for Smartcard ap-

plications.

Software development and firmware (ROM code,

options) generation are completed by the ST16-

19HDS development system.

The ST16CF54 Level B can be delivered either as

unsawn or sawn wafers, 180 or 275 micron thick-

ness as well as in micromodule package.

Figure 1 Block Diagram

SCP 096a/DS

MEMORY ACCESS CONTROL MATRIX

8 BIT

CPU

512

BYTES

SERIAL I/0's

INTERFACE

DATA

REGISTER

INTERNAL BUS

RAM

SECT.

A

SECT.

B

SECTOR

A

SECTOR

B

8K BYTES

SYSTEM

ROM

CRYPTO

LIBRARY

V

GENERATION

EEPROM 4K BYTES

SECTORS COMBINATIVE

I/O2

I/O1

CONTROL

REGISTER

SECURITY

LOGIC

WITH

NUMBER

GENERATOR

32/256/288/384/416/

RST

GND

VCC.

CLK

16K BYTES

USER ROM

SRAC

512 BIT MAP

PP