Preliminary Technical Data

AD7626

Rev. PrC | Page 9 of 11

THEORY OF OPERATION

Echoed-Clock Interface Mode

The AD7626 digital operation in “echoed-clock interface mode”

is shown in Figure 3. This interface mode, requiring just a shift

register on the digital host, can be used with many digital hosts

(FPGA, shift register, microprocessor, etc.). It requires 3 LVDS

pairs (D±, CLK±, and DCO±) between each AD7626 and the

digital host.

The clock DCO is a buffered copy of CLK and synchronous to

keeping good propagation delay matching between D and DCO

through the board and the digital host, DCO can be can be used

to latch D with good timing margin for the shift register.

Conversions are initiated by a CNV pulse. The CNV must be

conversion has begun, it continues until completion. Additional

CNV pulses are ignored during the conversion phase. After the

conversion result and should be used as the gating device for

CLK. The echoed clock, DCO, and data, D, will be driven in

phase with D being updated on the DCO+ falling edge and the

host should use the DCO+ rising edge to capture D. The only

requirement is that the 16 CLK pulses finish before the time

CLK+

TCYC

16

15

CNV+

116

15

2

1

23

TCNVH

TCLKL

DCO+

16

15

116

15

2

1

23

D+

SAMPLE N

SAMPLE N+1

D-

D15

N

D14

N

D1

N

CLK-

CNV-

DCO-

D0

N-1

ACQUISITION

ACQUISITION

ACQUISITION

TACQ

TDCO

TD

TCLK

0

TMSB

D1

N-1

D15

N+1

D14

N+1

D0

N

0

D13

N+1

TCLKD

Figure 3. Echoed-Clock Interface Mode Timing Diagram