BYTE WRITE

DEV SEL

BYTE ADDR

DATA IN

WC

PAGE WRITE

DEV SEL

BYTE ADDR

DATA IN 1

WC

DATA IN 2

AI01161B

PAGE WRITE

(cont'd)

WC (cont'd)

DATA IN N

ACK

ACK

NO ACK

R/W

ACK

ACK

NO ACK

R/W

NO ACK

NO ACK

Figure 9. Write Modes Sequence with Write Control = 1 (ST24/25W01)

Sequential Read. This mode can be initiated with

either a Current Address Read or a Random Ad-

dress Read. However, in this case the master

DOES acknowledge the data byte output and the

memory continues to output the next byte in se-

quence. To terminate the stream of bytes, the

master must NOT acknowledge the last byte out-

put, but MUST generate a STOP condition. The

output data is from consecutive byte addresses,

with the internal byte address counter automat-

ically incremented after each byte output. After a

count of the last memory address, the address

counter will ’roll- over’ and the memory will continue

to output data.

Acknowledge in Read Mode. In all read modes

the ST24/25x01 wait for an acknowledge during the

9th bit time. If the master does not pull the SDA line

low during this time, the ST24/25x01 terminate the

data transfer and switches to a standby state.

11/16

ST24/25C01, ST24C01R, ST24/25W01