Mode

RW bit

MODE pin

Bytes

Initial Sequence

Current Address Read

’1’

X

1

START, Device Select, RW = ’1’

Random Address Read

’0’

X1

START, Device Select, RW = ’0’, Address,

’1’

reSTART, Device Select, RW = ’1’

Sequential Read

’1’

X

1 to 2048

As CURRENT or RANDOM Mode

Byte Write

’0’

X

1

START, Device Select, RW = ’0’

Multibyte Write

’0’

8

START, Device Select, RW = ’0’

Page Write

’0’

16

START, Device Select, RW = ’0’

Table 4. Operating Modes

Device Code

Memory MSB Addresses

RW

Bit

b7

b6

b5

b4

b3

b2

b1

b0

Device Select

1

0

1

0

A10

A9

A8

RW

Note: The MSB b7 is sent first.

Table 3. Device Select Code

memory it responds to the 8 bits received by as-

serting an acknowledge bit during the 9th bit time.

When data is read by the bus master, it acknow-

ledges the receipt of the data bytes in the same

way. Data transfers are terminated with a STOP

condition.

Data in the 4 upper blocks of the memory may be

write protected. The protected area is programma-

ble to start on any 16 byte boundary. The block in

which the protection starts is selected by the input

pins PB0, PB1. Protection is enabled by setting a

Protect Flag bit when the PRE input pin is driven

High.

order to prevent data corruption and inadvertent

write operations during power up, a Power On

voltage has reached the POR threshold value, the

internal reset is active: all operations are disabled

and the device will not respond to any command.

operating voltage to below the POR threshold

value, all operations are disabled and the device

must be applied before applying any logic signal.

3/17

ST24/25C16, ST24/25W16