ICS251

FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER

EPROM CLOCK SYNTHESIZER

IDT™ / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 2

ICS251

REV B 061306

Pin Assignment

8-pin (150 mil) SOIC

Output Clock Selection Table

Pin Descriptions

External Components

The ICS251 requires a minimum number of external

components for proper operation.

Series Termination Resistor

Clock output traces over one inch should use series

termination. To series terminate a 50

Ω trace (a commonly

used trace impedance), place a 33

Ω resistor in series with

the clock line, as close to the clock output pin as possible.

The nominal impedance of the clock output is 20

Ω.

Decoupling Capacitor

As with any high-performance mixed-signal IC, the ICS251

must be isolated from system power supply noise to perform

optimally.

A decoupling capacitor of 0.01µF must be connected

between VDD and the PCB ground plane.

Crystal Load Capacitors

The device crystal connections should include pads for

small capacitors from X1 to ground and from X2 to ground.

These capacitors are used to adjust the stray capacitance of

the board to match the nominally required crystal load

capacitance. Because load capacitance can only be

increased in this trimming process, it is important to keep

stray capacitance to a minimum by using very short PCB

traces (and no vias) been the crystal and device. Crystal

capacitors must be connected from each of the pins X1 and

X2 to ground.

Example: For a crystal with a 16 pF load capacitance, each

crystal capacitor would be 20 pF [(16-6) x 2] = 20.

PCB Layout Recommendations

For optimum device performance and lowest output phase

noise, the following guidelines should be observed.

1) The 0.01µF decoupling capacitor should be mounted on

X1 / I C L K

VD D

G N D

S0

S1

CL K

X2

1

2

3

4

8

7

6

5

PD T S

S1

S0

CLK (MHz)

Spread

Percentage

0

0

User

Configurable

User

Configurable

01

User

Configurable

User

Configurable

10

User

Configurable

User

Configurable

11

User

Configurable

User

Configurable

Pin

Number

Pin

Name

Pin

Type

Pin Description

1

S0

Input

Select pin 0 for frequency selection on CLK. Internal pull-up resistor.

2

VDD

Power

Connect to +3.3 V.

3

X1/ICLK

XI

Connect this pin to a crystal or external clock input.

4

X2

XO

Connect this pin to a crystal, or float for clock input.

5

CLK

Output

Clock output. Weak internal pull-down when tri-state.

6

S1

Input

Select pin 1 for frequency selection on CLK. Internal pull-up resistor.

7

GND

Power

Connect this to Ground.

8PDTS

Input

Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up

resistor.