M48T08 datasheet(13/30 Pages) STMICROELECTRONICS

13 / 30 page

M48T08, M48T08Y, M48T18

Operation modes

13/30

When VCC drops below VSO, the control circuit switches power to the internal battery which

preserves data and powers the clock. The internal button cell will maintain data in the

M48T08/18/08Y for an accumulated period of at least 10 years when VCC is less than VSO.

Note:

Requires use of M4T32-BR12SH SNAPHAT® top when using the SOH28 package.

As system power returns and VCC rises above VSO, the battery is disconnected and the

power supply is switched to external VCC.

Write protection continues until VCC reaches VPFD (min) plus trec (min). E1 should be kept

high or E2 low as VCC rises past VPFD (min) to prevent inadvertent WRITE cycles prior to

system stabilization. Normal RAM operation can resume trec after VCC exceeds VPFD (max).

For more information on Battery Storage Life refer to the Application Note AN1012.

Power-fail interrupt pin

The M48T08/18/08Y continuously monitors VCC. When VCC falls to the power-fail detect trip

point, an interrupt is immediately generated. An internal clock provides a delay of between

10µs and 40µs before automatically deselecting the M48T08/18/08Y. The INT pin is an

open drain output and requires an external pull up resistor, even if the interrupt output

function is not being used.

M48T08 数据表(PDF) 13 Page - STMicroelectronics