ST5092AD datasheet(13/29 Pages) STMICROELECTRONICS

13 / 29 page

CONTROL REGISTER CR0

First byte of a READ or a WRITE instruction to

Control Register CR0 is as shown in TABLE 1.

Second byte is as shown in TABLE 2.

Master Clock Frequency Selection

A master clock must be provided to ST5092 for

operation of filter and coding/decodingfunctions.

MCLK frequency can be either 512 kHz, 1.536

MHz, 2.048 MHz or 2.56 MHz.

Bit F1 (7) and F0 (6) must be set during initializa-

tion to select the correct internal divider.

Default value is 512 kHz.

Any clock different from the default one must be

selected prior a Power-Up instruction.

Coding Law Selection

Bits MA (4) and IA (3) permit selection of Mu-255

law or A law coding with or without even bit inver-

sion if companded code (bit CM = 1) is selected.

Bits MA(4) and IA(3) permit selection of 2-com-

plement, 1-complement or sign and magnitude if

linear code (bit CM = 0) is selected.

Coding Selection

Bit CM (5) permits selection either of linear coding

(14-bit) or companded coding (8-bit). Default

value is linear coding.

Digital Interface format (1)

Bit FF(2) = 0 selects digital interface in Format 1

where B1 and B2 channel are consecutive. FF=1

selects Format 2 where B1 and B2 channel are

separated by two bits. (See digital interface for-

mat section.)

56+8 selection (1)

Bit ’B7’ (1) selects capability for ST5092 to take

into account only the seven most significant bits

of the PCM data byte selected.

When ’B7’ is set, the LSB bit on DR is ignored and

LSB bit on DX is high impedance. This function al-

lows connection of an external ”in band” data

generator directly connected on the Digital Inter-

face.

Digital loopback

Digital loopback mode is entered by setting DL

bit(0) equal 1.

In Digital Loopback mode, data written into Re-

ceive PCM Data Register from the selected re-

ceived time-slot is read-back from that Register in

the selected transmit time-slot on DX.

No PCM decoding or encoding takes place in this

mode. Transmit and Receive amplifier stages are

muted.

CONTROL REGISTER CR1

First byte of a READ or a WRITE instruction to

Control Register CR1 is as shown in TABLE 1.

Second byte is as shown in TABLE 3.

Digital Interface Timing

Bit DM1(7) = 0 selects digital interface in delayed

timing mode, while DM1 = 1 and DM0 = 0 selects

non-delayed normal data timing mode, and DM1

= 1 and DM0 = 1 selects non-delayed reverse

data timing mode.

Default is delayed data timing.

Latch output control

Bit DO controls directly logical status of latch out-

put LO: ie, a ”ZERO” written in bit DO puts the

output LO at logical 1, while a ”ONE” written in bit

DO sets the output LO to zero.

Microwire access to B channel on receive

path (1)

Bit MR (4) selects access from MICROWIRE

set high, data written to register CR2 is decoded

each frame, sent to the receive path and data in-

put at DR is ignored.

In the other direction, current PCM data input re-

ceived at DR can be read from register CR2 each

frame.

Microwire access to B channel on transmit

path (1)

Bit MX (3) selects access from MICROWIRE write

only Register CR3 to DX output. When bit MX is

set high, data written to CR3 is output at DX every

frame and the output of PCM encoder is ignored.

Mu 255 law

True A law even bit

inversion

A law without even bit

inversion

msb

lsb

msb

lsb

msb

lsb

Vin = + full scale

000000

101

1011

1111

Vin = 0 V

Vin = - full scale

000000

001

1001

1111

MSB is always the first PCM bit shifted in or out of: ST5092.

(1) Significant in companded mode only

ST5092

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