L9805E datasheet(21/127 Pages) STMICROELECTRONICS

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L9805E

Clocks, Reset, Interrupts & Power saving modes

21/127

Figure 8.

Timing Diagram for Internal CPU Clock Frequency transitions

3.2

Oscillator safeguard

The L9805E contains an oscillator safe guard function.

This function provides a real time check of the crystal oscillator generating a reset condition

when the clock frequency has anomalous value.

If fOSC<flow, a reset is generated.

If fOSC>fhigh, a reset is generated.

A flag in the Dedicated Control Status Register indicates if the last reset is a safeguard

reset.

At the output of reset state the safeguard is disable. To activate the safeguard SFGEN bit

must be set.

Note:

Following a reset, the safeguard is disabled. Once activated it cannot be disabled, except by

a reset.

3.2.1

Dedicated Control Status Register

DCSR

Address 0022h - Read/Write

Reset Value:xx00 0000 (00h)

b6 = SGFH: Safeguard high flag. Set by an Oscillator Safeguard Reset generated for

frequency too high, cleared by software (writing zero) or Power On / Low Voltage Reset.

b1 : b2

MISCELLANEOUS REGISTER

OSC/2

OSC/4

OSC/8

CPU CLK

VR02062B

New frequency

requested

New frequency

active when

osc/4 & osc/8 = 0

Normal mode active

(osc/4 - osc/8 stopped)

Normal mode

requested

SGFL

SGFH

SFGEN

CANDS

PIEN

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