TAS5414A datasheet(23/48 Pages) TI

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7-BitSlave Address

8-BitRegister Address(N)

8-BitRegisterDataFor

Address(N)

Start

Stop

SDA

SCL

8-BitRegisterDataFor

Address(N)

T0035-01

Random Write

R/W ACK A7

ACK

D0 ACK

Start

Condition

Stop

Condition

Acknowledge

I CDevice Addressand

Read/WriteBit

Subaddress

DataByte

T0036-01

Sequential Write

D0 ACK

Stop

Condition

Acknowledge

I CDevice Addressand

Read/WriteBit

Subaddress

LastDataByte

A0 R/W ACK A7

ACK D7

ACK

Start

Condition

Acknowledge

FirstDataByte

OtherDataBytes

ACK

Acknowledge

T0036-02

TAS5414A, TAS5424A

SLOS535A – JULY 2007 – REVISED FEBRUARY 2008

Figure 16. Typical I2C Sequence

Use the I2C_ADDR pin (pin 2) to program the device for one of four addresses. These four addresses are

licensed I2C addresses and do not conflict with other licensed I2C audio devices. To communicate with the

TAS5414A and the TAS5424A, the I2C master uses addresses shown in Figure 16. Read and write data can be

transmitted using single-byte or multiple-byte data transfers.

As shown in Figure 17, a single-byte data-write transfer begins with the master device transmitting a start

condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of

the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C device address

and the read/write bit, the TAS5414A or TAS5424A device responds with an acknowledge bit. Next, the master

transmits the address byte or bytes corresponding to the internal memory address being accessed. After

receiving the address byte, the TAS5414A or TAS5424A again responds with an acknowledge bit. Next, the

master device transmits the data byte to be written to the memory address being accessed. After receiving the

data byte, the TAS5414A or TAS5424A again responds with an acknowledge bit. Finally, the master device

transmits a stop condition to complete the single-byte data-write transfer.

Figure 17. Random Write Transfer

A sequential data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes are

transmitted by the master device to TAS5414A or TAS5424A as shown in Figure 17. After receiving each data

byte, the TAS5414A or TAS5424A responds with an acknowledge bit and the I2C subaddress is automatically

incremented by one.

Figure 18. Sequential Write Transfer

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