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CAT5259 数据表(PDF) 5 Page - Catalyst Semiconductor

部件名 CAT5259
功能描述  Quad Digitally Programmable Potentiometers (DPP?? with 256 Taps and I짼C Interface
PDF  16 Pages
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制造商  CATALYST [Catalyst Semiconductor]
网页  http://www.catalyst-semiconductor.com
标志 CATALYST - Catalyst Semiconductor

CAT5259 数据表(HTML) 5 Page - Catalyst Semiconductor

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CAT5259
© Catalyst Semiconductor, Inc.
5
Doc. No. MD-2000 Rev. H
Characteristics subject to change without notice
POWER UP TIMING
(1)(2)
Symbol
Parameter
Max
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
XDCP TIMING
Symbol
Parameter
Min
Max
Units
tWRPO
Wiper Response Time After Power Supply Stable
5
10
µs
tWRL
Wiper Response Time After Instruction Issued
5
10
µs
WRITE CYCLE LIMITS
(3)
Symbol
Parameter
Max
Units
tWR
Write Cycle Time
5
ms
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Max
Units
NEND
(4)
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
TDR
(4)
Data Retention
MIL-STD-883, Test Method 1008
100
Years
VZAP
(4)
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
V
ILTH
(4)
Latch-Up
JEDEC Standard 17
100
mA
Figure 1. Bus Timing
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are delays required from the time VCC is stable until the specified operation can be initiated.
(3) The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
tHIGH
SCL
SDA IN
SDAOUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH



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