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ST62T32B 数据表(PDF) 31 Page - STMicroelectronics |
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ST62T32B 数据表(HTML) 31 Page - STMicroelectronics |
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31 / 86 page  31/86 ST62T32B ST62E32B INTERRUPTS (Cont’d) 3.4.3 Interrupt Option Register (IOR) The Interrupt Option Register (IOR) is used to en- able/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. This register is write-only and cannot be accessed by single-bit operations. Address: 0C8h — Write Only Reset status: 00h Bit 7, Bits 3-0 = Unused. Bit 6 = LES: Level/Edge Selection bit. When this bit is set to one, the interrupt source #1 is level sensitive. When cleared to zero the edge sensitive mode for interrupt request is selected. Bit 5 = ESB: Edge Selection bit. The bit ESB selects the polarity of the interrupt source #2. Bit 4 = GEN: Global Enable Interrupt. When this bit is set to one, all interrupts are enabled. When this bit is cleared to zero all the interrupts (excluding NMI) are disabled. When the GEN bit is low, the NMI interrupt is ac- tive but cannot cause a wake up from STOP/WAIT modes. This register is cleared on reset. 3.4.4 IInterrupt sources Interrupt sources available on the ST62E32B/T32B are summarized in theTable 11 with associated mask bit to enable/disable the in- terrupt request. Table 11. Interrupt Requests and Mask Bits 70 - LES ESB GEN - - - - Peripheral Register Address Register Mask bit Masked Interrupt Source Interrupt source GENERAL IOR C8h GEN All Interrupts, excluding NMI All TIMER TSCR1 D4h ETI TMZ: TIMER Overflow source 4 A/D CONVERTER ADCR D1h EAI EOC: End of Conversion source 4 UART UARTCR D7h RXIEN TXIEN RXRDY : Byte received TXMT : Byte sent source 4 ARTIMER SCR1 SCR2 SCR3 SCR3 SCR3 E8h E1h E2h E2h E2h OVFIEN CP1IEN CP2IEN ZEROIEN CMPIEN OVFFLG: ARTIMER Overflow CP1FLG CP2FLG ZEROFLG: Compare to zero flag CMPFLG: Compare flag source 3 SPI SPI DCh ALL End of Transmission source 1 Port PAn ORPA-DRPA C0h-C4h ORPAn-DRPAn PAn pin source 1 Port PBn ORPB-DRPB C1h-C5h ORPBn-DRPBn PBn pin source 2 Port PCn ORPC-DRPC C2h-C6h ORPCn-DRPCn PCn pin source 0 Port PDn ORPD-DRPD C3h-C7h ORPDn-DRPDn PDn pin source 2 Port PEn ORPE-DRPE FCh-FDh ORPEn-DRPEn PEn pin source 1 135 |
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