M95040, M95020, M95010

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Read from Memory Array (READ)

As shown in Figure 12., to send this instruction to

the device, Chip Select (S) is first driven Low. The

bits of the instruction byte and address byte are

then shifted in, on Serial Data Input (D). For the

M95040, the most significant address bit, A8, is in-

corporated as bit b3 of the instruction byte, as

shown in Table 5.. The address is loaded into an

internal address register, and the byte of data at

that address is shifted out, on Serial Data Output

(Q).

If Chip Select (S) continues to be driven Low, an

internal bit-pointer is automatically incremented at

each clock cycle, and the corresponding data bit is

shifted out.

When the highest address is reached, the address

counter rolls over to zero, allowing the Read cycle

to be continued indefinitely. The whole memory

can, therefore, be read with a single READ instruc-

tion.

The Read cycle is terminated by driving Chip Se-

lect (S) High. The rising edge of the Chip Select

(S) signal can occur at any time during the cycle.

The first byte addressed can be any byte within

any page.

The instruction is not accepted, and is not execut-

ed, if a Write cycle is currently in progress.

Table 6. Address Range Bits

Figure 12. Read from Memory Array (READ) Sequence

Note: Depending on the memory size, as shown in Table 6., the most significant address bits are Don’t Care.

Device

M95040

M95020

M95010

Address Bits

A8-A0

A7-A0

A6-A0

C

D

AI01440E

S

Q

A7

2

1

3456789 10 11 12 13 14 15 16 17 18 19

A6 A5 A4 A3 A2 A1 A0

A8

20 21 22

76543

2

0

1

High Impedance

Data Out

Instruction

Byte Address

0