ST62T53B datasheet(38/75 Pages) STMICROELECTRONICS

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ST62T53B/T60B/T63B ST62E60B

4.2 TIMER

The MCU features an on-chip Timer peripheral,

consisting of an 8-bit counter with a 7-bit program-

mable prescaler, giving a maximum count of 215.

Figure 22 shows the Timer Block Diagram. The

content of the 8-bit counter can be read/written in

the Timer/Counter register, TCR, which can be ad-

dressed in Data space as a RAM location at ad-

dress 0D3h. The state of the 7-bit prescaler can be

read in the PSC register at address 0D2h. The

control logic device is managed in the TSCR reg-

ister as described in the following paragraphs.

The 8-bit counter is decrement by the output (ris-

ing edge) coming from the 7-bit prescaler and can

be loaded and read under program control. When

it decrements to zero then the TMZ (Timer Zero)bit

in the TSCR is set. If the ETI (Enable Timer Inter-

rupt) bit in the TSCR is also set, an interrupt re-

quest is generated. The Timer interrupt can be

used to exit the MCU from WAIT mode.

The prescaler input is the internal frequency (fINT)

divided by 12. The prescaler decrements on the

rising edge. Depending on the division factor pro-

grammed by PS2, PS1 and PS0 bits in the TSCR

(see Figure 14), the clock input of the timer/coun-

ter register is multiplexed to different sources. For

division factor 1, the clock input of the prescaler is

also that of timer/counter; for factor 2, bit 0 of the

prescaler register is connected to the clock input of

TCR. This bit changes its state at half the frequen-

cy of the prescaler input clock. For factor 4, bit 1 of

the PSC is connected to the clock input of TCR,

and so forth. The prescaler initialize bit, PSI, in the

TSCR register must be set to allow the prescaler

(and hence the counter) to start. If it is cleared, all

the prescaler bits are set and the counter is inhib-

ited from counting. The prescaler can be loaded

with any value between 0 and 7Fh, if bit PSI is set.

The prescaler tap is selected by means of the

PS2/PS1/PS0 bits in the control register.

Figure 23 illustrates the Timer’s working principle.

Figure 22. Timer Block Diagram

STATUS/CONTROL

TMZ ETI

PSI PS2 PS1 PS0

8-BIT

1OF 7

SELECT

INTERRUPT

LINE

PSC

VR02070A

INT

b2 b1

DATA BUS

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