ST62T55B datasheet(38/74 Pages) STMICROELECTRONICS

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ST62T55B ST62T65B/E65B

4.2 TIMER

The MCU features an on-chip Timer peripheral,

consisting of an 8-bit counter with a 7-bit program-

mable prescaler, giving a maximum count of 215.

The peripheral may be configured in three different

operating modes.

21 shows the Timer Block Diagram. The external

TIMER pin is available to the user. The content of

the 8-bit counter can be read/written in the Timer/

Counter register, TCR, while the state of the 7-bit

prescaler can be read in the PSC register. The

control logic device is managed in the TSCR reg-

ister as described in the following paragraphs.

The 8-bit counter is decremented by the output

(rising edge) coming from the 7-bit prescaler and

can be loaded and read under program control.

When it decrements to zero then the TMZ (Timer

Zero) bit in the TSCR is set to “1”. If the ETI (Ena-

ble Timer Interrupt) bit in the TSCR is also set to

“1”, an interrupt request is generated as described

in the Interrupt Chapter. The Timer interrupt can

be used to exit the MCU from WAIT mode.

The prescaler input can be the internal frequency

fINT divided by 12 or an external clock applied to

the TIMER pin. The prescaler decrements on the

rising edge. Depending on the division factor pro-

grammed by PS2, PS1 and PS0 bits in the TSCR.

The clock input of the timer/counter register is mul-

tiplexed to different sources. For division factor 1,

the clock input of the prescaler is also that of timer/

counter; for factor 2, bit 0 of the prescaler register

is connected to the clock input of TCR. This bit

changes its state at half the frequency of the pres-

caler input clock. For factor 4, bit 1 of the PSC is

connected to the clock input of TCR, and so forth.

The prescaler initialize bit, PSI, in the TSCR regis-

ter must be set to “1” to allow the prescaler (and

hence the counter) to start. If it is cleared to “0”, all

the prescaler bits are set to “1” and the counter is

inhibited from counting. The prescaler can be

loaded with any value between 0 and 7Fh, if bit

PSI is set to “1”. The prescaler tap is selected by

means of the PS2/PS1/PS0 bits in the control reg-

ister.

22 illustrates the Timer’s working principle.

Figure 21. Timer Block Diagram

DATABUS 8

8-BIT

COUNTER

PSC

STATUS/CONTROL

b 5

b 2

b 1

TMZ

ET I

TO UT

DOUT

PSI

PS2

PS1

P S0

SELECT

1OF 7

LATCH

SYNCHRONIZATION

LOGIC

TIMER

INTERRUPT

LINE

VA00009

:12

fOSC

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