ST6387 datasheet(16/84 Pages) STMICROELECTRONICS

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ST6365, ST6375, ST6385 ST6367, ST6377, ST6387

2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION

The CPU Core of ST6 devices is independent of the

I/O or Memory configuration. As such, it may be

thought of as an independent central processor

communicating with on-chip I/O, Memory and Pe-

ripherals via internal address, data, and control

buses. In-core communication is arranged as

shown in Figure 8; the controller being externally

linked to both the Reset and Oscillator circuits,

while the core is linked to the dedicated on-chip pe-

ripherals via the serial data bus and indirectly, for

interrupt purposes, through the control registers.

2.2 CPU REGISTERS

The ST6 Family CPU core features six registers

and three pairs of flags available to the program-

mer. These are described in the following para-

graphs.

Accumulator (A). The accumulator is an 8-bit

general purpose register used in all arithmetic cal-

culations, logical operations, and data manipula-

tions. The accumulator can be addressed in Data

space as a RAM location at address FFh. Thus the

ST6 can manipulate the accumulator just like any

other register in Data space.

Indirect Registers (X, Y). These two indirect reg-

isters are used as pointers to memory locations in

Data space. They are used in the register-indirect

addressing mode. These registers can be ad-

dressed in the data space as RAM locations at ad-

dresses 80h (X) and 81h (Y). They can also be ac-

cessed with the direct, short direct, or bit direct ad-

dressing modes. Accordingly, the ST6 instruction

set can use the indirect registers as any other reg-

ister of the data space.

Short Direct Registers (V, W). These two regis-

ters are used to save a byte in short direct ad-

dressing mode. They can be addressed in Data

space as RAM locations at addresses 82h (V) and

83h (W). They can also be accessed using the di-

rect and bit direct addressing modes. Thus, the

ST6 instruction set can use the short direct regis-

ters as any other register of the data space.

Program Counter (PC). The program counter is a

12-bit register which contains the address of the

next ROM location to be processed by the core.

This ROM location may be an opcode, an oper-

and, or the address of an operand. The 12-bit

length allows the direct addressing of 4096 bytes

in Program space.

Figure 8. ST6 Core Block Diagram

PROGRAM

RESET

OPCODE

FLAG

VALUES

CONTROLLER

FLAGS

ALU

A-DATA

B-DATA

ADDRESS/READ LINE

DATA SPACE

INTERRUPTS

DATA

RAM/EEPROM

DATA

ROM/EPROM

RESULTS TO DATA SPACE (WRITE LINE)

ROM/EPROM

DEDICATIONS

ACCUMULATOR

CONTROL

SIGNALS

OSCin

OSCout

ADDRESS

DECODER

256

Program Counter

and

6 LAYER STACK

0,01 TO 8MHz

VR01811

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