ST72104G2 datasheet(104/135 Pages) STMICROELECTRONICS

104 / 135 page

ST72104G, ST72215G, ST72216G, ST72254G

104/135

13.5 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for VDD,fOSC, and TA.

13.5.1 General Timings

13.5.2 External Clock Source

Figure 63. Typical Application with an External Clock Source

Notes:

1. Data based on typical application software.

2. Time measured between interrupt event and interrupt vector fetch.

∆t

c(INST) is the number of tCPU cycles needed to finish

the current instruction execution.

3. Data based on design simulation and/or technology characteristics, not tested in production.

Symbol

Parameter

Conditi ons

Min

Typ 1)

Max

Unit

tc(INST)

Instruction cycle time

tCPU

fCPU=8MHz

250

375

1500

tv(IT)

Interrupt reaction time 2)

tv(IT) = ∆tc(INST) +10

tCPU

fCPU=8MHz

1.25

2.75

µs

Symbol

Parameter

Condi tions

Min

Typ

Max

Unit

VOSC1H

OSC1 input pin high level voltage

see Figure 63

0.7xVDD

VDD

VOSC1L

OSC1 input pin low level voltage

VSS

0.3xVDD

tw(OSC1H)

tw(OSC1L)

OSC1 high or low time 3)

tr(OSC1)

tf(OSC1)

OSC1 rise or fall time 3)

OSCx Input leakage current

VSS≤VIN≤VDD

±1

µA

OSC1

OSC2

fOSC

EXTERNAL

ST72XXX

CLOCK SOURCE

Not connected internally

VOSC1L

VOSC1H

tr(OSC1)

tf(OSC1)

tw(OSC1H)

tw(OSC1L)

90%

10%

ST72104G2 数据表(PDF) 104 Page - STMicroelectronics

ST72104G2 数据表(HTML) 104 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载