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ST72321 数据表(PDF) 128 Page - STMicroelectronics

部件名 ST72321
功能描述  8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE
PDF  185 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST72321 数据表(HTML) 128 Page - STMicroelectronics

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10-BIT A/D CONVERTER (ADC) (Cont’d)
10.8.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read /Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
Bit 7 = EOC
End of Conversion
This bit is set by hardware. It is cleared by hard-
ware when software reads the ADCDRH register
or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED
ADC clock selection
This bit is set and cleared by software.
0: fADC = fCPU/4
1: fADC = fCPU/2
Bit 5 = ADON
A/D Converter on
This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
Bit 4 = Reserved. Must be kept cleared.
Bit 3:0 = CH[3:0]
Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
*The number of channels is device dependent. Refer to
the device pinout description.
DATA REGISTER (ADCDRH)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:0 = D[9:2]
MSB of Converted Analog Value
DATA REGISTER (ADCDRL)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:2 = Reserved. Forced by hardware to 0.
Bit 1:0 = D[1:0]
LSB of Converted Analog Value
70
EOC
SPEED ADON
0
CH3
CH2
CH1
CH0
Channel Pin*
CH3
CH2
CH1
CH0
AIN0
0
0
0
0
AIN1
0
0
0
1
AIN2
0
0
1
0
AIN3
0
0
1
1
AIN4
0
1
0
0
AIN5
0
1
0
1
AIN6
0
1
1
0
AIN7
0
1
1
1
AIN8
1
0
0
0
AIN9
1
0
0
1
AIN10
1
0
1
0
AIN11
1
0
1
1
AIN12
1
1
0
0
AIN13
1
1
0
1
AIN14
1
1
1
0
AIN15
1
1
1
1
70
D9
D8
D7
D6
D5
D4
D3
D2
70
000
000
D1
D0



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