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ST72321 数据表(PDF) 37 Page - STMicroelectronics |
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ST72321 数据表(HTML) 37 Page - STMicroelectronics |
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37 / 185 page  ST72321 37/185 INTERRUPTS (Cont’d) Table 7. Interrupt Mapping Notes: 1. Valid for HALT mode except for the MCC/RTC or CSS interrupt source which exits from ACTIVE-HALT mode. 2. Exit from HALT possible when SPI is in slave mode. 3. Exit from HALT possible when PWM ART is in external clock mode. 7.6 EXTERNAL INTERRUPTS 7.6.1 I/O Port Interrupt Sensitivity The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR register (Figure 22). This control allows to have up to 4 fully independent external interrupt source sensitivities. Each external interrupt source can be generated on four (or five) different events on the pin: s Falling edge s Rising edge s Falling and rising edge s Falling edge and low level s Rising edge and high level (only for ei0 and ei2) To guarantee correct functionality, the sensitivity bits in the EICR register can be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that interrupts must be disabled before changing sensitivity. The pending interrupts are cleared by writing a dif- ferent value in the ISx[1:0], IPA or IPB bits of the EICR. N° Source Block Description Register Label Priority Order Exit from HALT1) Address Vector RESET Reset N/A yes FFFEh-FFFFh TRAP Software interrupt no FFFCh-FFFDh 0 TLI External top level interrupt EICR yes FFFAh-FFFBh 1 MCC/RTC CSS Main clock controller time base interrupt Safe oscillator activation interrupt MCCSR SICSR Higher Priority yes FFF8h-FFF9h 2 ei0 External interrupt port A3..0 N/A yes FFF6h-FFF7h 3 ei1 External interrupt port F2..0 yes FFF4h-FFF5h 4 ei2 External interrupt port B3..0 yes FFF2h-FFF3h 5 ei3 External interrupt port B7..4 yes FFF0h-FFF1h 6 Not used FFEEh-FFEFh 7 SPI SPI peripheral interrupts SPICSR yes2 FFECh-FFEDh 8 TIMER A TIMER A peripheral interrupts TASR no FFEAh-FFEBh 9 TIMER B TIMER B peripheral interrupts TBSR no FFE8h-FFE9h 10 SCI SCI Peripheral interrupts SCISR Lower Priority no FFE6h-FFE7h 11 AVD Auxiliary Voltage detector interrupt SICSR no FFE4h-FFE5h 12 I2C I2C Peripheral interrupts (see periph) no FFE2h-FFE3h 13 PWM ART PWM ART interrupt ARTCSR yes3 FFE0h-FFE1h |
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