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ST72321 数据表(PDF) 181 Page - STMicroelectronics |
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ST72321 数据表(HTML) 181 Page - STMicroelectronics |
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181 / 185 page  ST72321 181/185 15.3 FLASH REV “S” and ALL ROM DEVICES 15.3.1 External clock source with PLL External clock source is not supported with the PLL enabled. 15.3.2 LVD Startup behaviour When the LVD is enabled, the MCU reaches its authorized operating voltage from a reset state. However, in some devices, the reset state is re- leased when VDD is approximately between 0.8V and 1.5V. As a consequence, the I/Os may toggle when VDD is within this window. This may be an issue especially for applications where the MCU drives power components. Because Flash write access is impossible within this window, the Flash memory contents will not be corrupted. Figure 111. LVD Startup Behaviour 5V 1.5V VIT+ 0.8V LVD RESET V D D Window t |
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