ST72C171 datasheet(17/152 Pages) STMICROELECTRONICS

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ST72C171

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4.2.1 Reset Sequence Manager (RSM)

The RSM block of the CROSS Module includes

three RESET sources as shown in Figure 10:

EXTERNAL RESET SOURCE pulse

Internal LVD RESET (Low Voltage Detection)

Internal WATCHDOG RESET

These sources act on the RESET PIN and it is al-

ways kept low during the READ OPTION RESET

phase.

The RESET service routine vector is fixed at the

FFFEh-FFFFh addresses in the ST7 memory

map.

Figure 10. Reset Block Diagram

The basic RESET sequence consists of 4 phases

as shown in Figure 11:

OPTION BYTE reading to configure the device

Delay depending on the RESET source

4096 cpu clock cycle delay

RESET vector fetch

The duration of the OPTION BYTE reading phase

(tROB) is defined in the Electrical Characteristics

section. This first phase is initiated by an external

RESET pin pulse detection, a Watchdog RESET

detection, or when VDD rises up to VLVDopt.

The 4096 cpu clock cycle delay allows the oscilla-

tor to stabilise and to ensure that recovery has tak-

en place from the Reset state.

The RESET vector fetch phase duration is 2 clock

cycles.

Figure 11. RESET Sequence Phases

fCPU

RESET

RON

VDD

WATCHDOG RESET

LVD RESET

INTERNAL

RESET

READ OPTION RESET

RESET

READ

OPTION BYTE

INTERNAL RESET

4096 CLOCK CYCLES

FETCH

VECTOR

DELAY

tROB

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