ST72E121 datasheet(44/92 Pages) STMICROELECTRONICS

44 / 92 page

44/92

ST72E121 ST72T121

16-BIT TIMER (Cont’d)

4.3.4 Low Power Modes

4.3.5 Interrupts

Note: The 16-bit Timer interrupt events are con-

nected to the same interrupt vector (see Interrupts

chapter).

These events generate an interrupt if the corre-

sponding Enable Control Bit is set and the I-bit in

the CC register is reset (RIM instruction).

Mode

Description

WAIT

No effect on 16-bit Timer.

Timer interrupts cause the device to exit from WAIT mode.

HALT

16-bit Timer registers are frozen.

In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous

count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter

reset value when the MCU is woken up by a RESET.

If an input capture event occurs on the ICAP

i pin, the input capture detection circuitry is armed. Consequent-

ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICF

i bit is set, and

the counter value present when exiting from HALT mode is captured into the IC

iR register.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

Input Capture 1 event/Counter reset in PWM mode

ICF1

ICIE

Yes

Input Capture 2 event

ICF2

Yes

Output Compare 1 event (not available in PWM mode)

OCF1

OCIE

Yes

Output Compare 2 event (not available in PWM mode)

OCF2

Yes

Timer Overflow event

TOF

TOIE

Yes

ST72E121 数据表(PDF) 44 Page - STMicroelectronics

ST72E121 数据表(HTML) 44 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

数据表下载