2 - Receive Section

The receive section is active when Rx/Tx = 1.

The baud rate and channel selection is also made

according to Table 1.

The Rx signal is applied on RAI with a common

mode voltage of 0V and filtered by a band-pass

switched capacitor filter (Rx band-pass) centered

on the received carrier frequency and whose band-

width is around 6kHz. The input voltage range on

The Rx filter output is amplifiedby a 20dBgain stage

whichprovidessymmetrical limitations forlarge volt-

age. The resulting signal is down-converted by a

mixer which receives a local oscillator synthesized

by the FSK modulator block. Finally an intermediate

frequency band-pass filter (IF band-pass) whose

central frequency is 2.7kHz when BRS = 0 and

5.4kHz when BRS = 1 improves the signal to noise

ratio before entering the FSK demodulator. The

coupling of the intermediate frequency filter output

(IFO) to the FSKdemodulatorinput (DEMI) is made

by an externalcapacitor C5 (1

µF ±10%,10V) which

cancels the Rx path offset voltage.

A clock recovery circuit extracts the receive clock

(CLR/T) from the demodulated output (RxDEM)

and delivers synchronous data (RxD) on the posi-

tive edge of CLR/T.

FUNCTIONAL DESCRIPTION (continued)

3 - Additional Digital and Analog Functions

A reset intput (RESET) initializes the device.

When RESET = 0, the device is in power-down

mode and all the internal logic is reset. When

RESET = 1, the device is active.

A time base section delivers all the internal clocks

from a crystal oscillator (11.0592MHz). The crystal

is connected between XTAL1 and XTAL2 pins and

needs two external capacitors C3 and C4 depend-

ing o n t he cryst al ch ara cte ristic typically

22pF

±10% for proper operation. It is also possible

to provide directly the clock on pin XTAL1 ; in this

case C3 and C4 should be removed.

An Automatic Frequency Control (AFC) Section

adjusts the central frequency of Rx and Tx band-

pass filter to the carrier central frequency. The

stability of the AFC loop is ensured by an external

compensation network C1 (470nF

±10%, 10V), C2

CLR/T

RxD

DATA VALID

Figure 3 : Rx Data Output Timing

(47nF

±10%, 10V) and R1 (1.5kΩ ±5%) connected

to pin AFCF.

17

C1

C2

R1

AFCF

AGND

22

Figure 4 : Automatic Frequency Loop Filter

4 - Testing Features

- An additionnalamplifier allows the observationof

the Rx band-pass filter output on pin RxFO.

- A direct input to the Tx band-pass filter (TxFI) is

available and selected when TEST4 = 1.

- The 3 second normal duration of the Tx to Rx

mode automatic switching is reduced to 1.48ms

when TEST2 = 1.

- When TEST1 = 1 the Tx to Rx mode automatic

switching is desactivated and the functional mode

of the circuit is controlledby Rx/Tx as follow : when

Rx/Tx = 0 the circuit is transmitting continuously,

whenRx/Tx = 1 the clock recovery block is discon-

nected from the FSK demodulator for testing pur-

pose, in this configuration TEST 3 is the data input

of the clock recovery block, RxDEM follow TEST3

and RxD delivers the resynchronized data.

5 - Power Supplies Wiring and Decoupling

Precautions

The ST7536 has two positive power supply pins,

two negative power supply pins and two ground

pins in order to separate internal analog and digital

supplies. The analog and digital terminals of each

supply pair must be connected together externally

and require special routing precautions in order to

get the best receive sensitivity performances.

The three major routing requirements are :

- The ground impedance should be as low as

possible, for this purpose the AGND an DGND

terminals can be connected via a local plane.

avoiding common current path for the digital and

analog power supplies terminals.

- Five decoupling capacitors located as close as

possible to the power supply terminals should be

used. Two 2.2

µF tantalum and two 100nF ce-

ramic capacitors perform the main decoupling

function in the vicinity of the analog power sup-

plies and a 100nFceramic capacitor in the vicinity

of the positive digital power supply is used to

reduce the high frequency perturbations gener-

ated by the logic part of the circuit.

ST7536

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