3 - Reset, Powerdown (RESET, PDOWN)

RESET Pin initialises the internal counters and

control registers to their default value. A minimum

low pulse of 1ms is required to reset the chip.

In a typical application RESET is connected to

VBUS through a R, C network. This ensures that

the chip is reset at each connection / disconnection

to the USB bus (see Figure 3).

PDOWN Pin shall be connected to the powerdown

inputs of the external codec used on the SSI.

When ST7554 is in Suspend mode, PDOWN is

forced low so that the external codec is in

powerdown.

PIN DESCRIPTION (continued)

12 RESET

R

220k

W

C

10nF

VBUS

Figure 3 : RC network for RESET

9

10

R

1.8k

W

C

18pF

C

18pF

AGND

AGND

XTAL

OUT

XTAL

IN

Figure 4 :

Application schematic for the

9.216MHz external crystal

4 - Serial Synchronous Interface

ST7554 has a Serial Syncronous Interface (SSI)

dedicated to the connection of the STLC7550 or

ST75951, ST high performance Modem Analog

Front-End (MAFE).

4.1 - Data (DIN, DOUT)

Digital data word input/output of SSI, to be con-

nected to the data word pins of STLC7550 or

ST75951.

4.2 - Master Clock (MCLK)

This pin is the master clock output.

4.3 - Frame Synchronization (FS)

The frame synchronization is used to synchronize data

transfer between ST7554 and the external Codec.

4.4 - Hardware Control (HC1)

HC1 must be connected to the corresponding pin of

STLC7550 or ST75951, while their HC0 Pin shall be

tied to the 3.3V VREGD digital supply. This pin

selects data or control modes for the Modem Codec.

4.5 - DAA Selection (DAASEL)

Connect to VREGD when using silicon DAA chipset

based on ST75951 + ST952. Connect to DGND

when using STLC7550 with discrete interface.

5 - DAA Control Pins (IMP, DC, BUZEN,

PULSE, DISHS, RFC, LED, CLID, HO, HSDT, RI)

These pins control the World Wide software

programmable DAA through ST75951/ST952.

6 - Crystal (XTALIN, XTALOUT)

These pins must be tied to the 9.216MHz external

crystal.

It is recommended to use a

±50ppm fundamental

parallel resonator crystal. It is recommended to

insert a 1.8k

Ω resistor between XTALOUT and the

crystal to limit its energy to 100

µW for a 20Ω

resonator (see Figure 4).

For a SMD crystal the load capacitor is typically

C = 24pF for the capacitors between the crystal

and analog ground (AGND). Anyway, in practice

these capacitors shall be reduced down to

C = 18pF each by considering parasitic capacitors

on PCB and package (see Figure 4).

After a reset or when leaving the suspend state,

the 9.216MHz is asserted inside ST7554 only

3.5ms later in order to wait for it to be stable.

7 - PLL Output Filter (FLTPLL)

This pin must be connected to the analog ground

(AGND) through a 33pF capacitor.

8 - Reserved Pins (18 pins)

These pins must be left not connected except

Pin 47 which should be connected to the digital

ground DGND.

ST7554

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